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CMOS Integrated Circuits–II Circuit Design Project

Just captions/titles/figures/tables… no writing in this project submission (see project example).

Design a fully differential operational amplifier meeting the following specifications. And also complete the IC layout of the opamp that passes DRC and LVS. Everything is to be done in the Cadence environment using the TSMC 0.18um setup. Use an ideal power supply (1.8±0.1V), an ideal common-mode voltage reference of your choosing (fixed for all cases), and an ideal reference current source to ground (fixed for all cases). If you use resistors, the nominal value must be less than or equal to 25kW. Finally, you are not allowed to use RHP zero cancellation in this project. Simulations are to be completed for three process corners: TT (with temp=27ºC & VDD=1.8V), SS (with temp=85ºC & VDD=1.7V), and FF (with temp=-40ºC & VDD=1.9V).

Specifications (for all three cases): Power supply VDD=1.8V, 1.7V, 1.9V (TT, SS, FF) Load at each output Cload=3pF (to be affected by TT, SS, FF) Loop gain > 70 dB Loop UGBW > 70 MHz Loop Phase Margin > 60° CMFB Phase Margin > 60° CM accuracy (with no differential signal) < ±0.05V Output swing (6dB/50% compression) > 1V peak-to-peak differential Power consumption (including bias) < 9 mW Differential Loop characteristics are to be obtained with 1pF input and feedback capacitors (fixed 1pF value for all cases). Use 1GW resistors as needed for simulation purposes. Eliminate the 1pF input/feedback capacitors when doing CMFB evaluation. About a 2/3 of your project grade will depend on this design and simulation portion. The second part of the project is IC layout. Grading depends on whether you pass LVS and DRC, and the quality of your layout (ask yourself if the layout “looks” good). About a 1/3 of project grading will depend on this layout portion.

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